Description #
VHDL (VHSIC Hardware Description Language) is a compiled language used to model and simulate digital electronic systems, particularly those implemented on FPGAs and ASICs. It enables designers to describe hardware behavior and structure at various abstraction levels.
History #
VHDL was developed in the early 1980s under a U.S. Department of Defense initiative for the VHSIC (Very High Speed Integrated Circuit) program. The first version was released in 1985, and it became an IEEE standard in 1987 (IEEE 1076). Unlike software languages, VHDL was designed to simulate hardware timing and concurrency, and to support synthesis to real silicon circuits.
Hello World Code #
library ieee;
use ieee.std_logic_1164.all;
entity HelloWorld is
end HelloWorld;
architecture behavior of HelloWorld is
begin
process
begin
report "Hello, World!";
wait;
end process;
end behavior;How to Run #
Option 1: Online
https://www.edaplayground.com/x/kWWd
Option 2: Local
- Install GHDL
- Save as
hello.vhdland run:
ghdl -a hello.vhdl
ghdl -e HelloWorld
ghdl -r HelloWorldKey Concepts #
- Syntax style: Ada-like, strongly typed, verbose
- Typing discipline: Static, with user-defined types and bit-level precision
- Execution model: Event-driven simulation; compiles to netlists or logic gates
- Common use cases: FPGA/ASIC design, simulation, hardware verification
- Toolchain or ecosystem: GHDL, ModelSim, Vivado, Quartus
- Paradigms supported: Structural, behavioral, dataflow modeling
- Compilation details: Analyzed and elaborated into simulation models or synthesized circuits
- Strengths or quirks: Strong typing for hardware safety, support for testbenches
- Libraries/frameworks: IEEE std_logic_1164, std_logic_arith, numeric_std
- Community/adoption: Widely used in academia, defense, and hardware engineering
Try It Online #
Fun Facts #
VHDL can model hardware at very low (gate-level) or high (algorithmic) abstraction levels. The language is so precise that entire CPUs, GPUs, and SoCs are described in it before ever being fabricated.
